DVASM Listing for Input File: /TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/examples/riscv-heapsort/dvasmsortlong.asm
DVASM execution completed on: Wed Aug 30 22:44:15 EDT 2023
--- Log Start
Framework JAR file is [file:/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/code-and-manuals/dvasm.v1-r0.1.jar]
User macro directory[1] is: [/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/examples/riscv-heapsort]
Architecture JAR file selected is [file:/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/code-and-manuals/dvasm.v1-r0.1.jar]
No architecture extension used
Parse elapsed time is: 1392 milliseconds
Input parsing completed succesfully
Dependencies preprocessing completed successfully
Dependencies resolution completed successfully
Code generation completed successfully
Dependencies resolution completed successfully
Code generation completed successfully
Code generation elapsed time is: 73 milliseconds
--- Log End
1 | //--------------------------------------------------------------------------------------------------
2 | //
3 | // @ CopyRight Roberti & Parau Enterprises, Inc. 2021-2023
4 | //
5 | // This work is licensed under the Creative Commons Attribution 4.0 International License.
6 | // To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/
7 | // or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
8 | //
9 | //--------------------------------------------------------------------------------------------------
10 | //
11 | // This code sort a vector of 64 bits integers in ascending order.
12 | // The code uses macro HEAPSORT from the standard DaVinci assembler RISC-V module.
13 | // It can be called as a function by C code generated by the GNU compiler
14 | // or any GNU compatible compiler
15 | //
16 | // The code is divided into two sections:
17 | //
18 | // 1. The macro that carries out all integer comparisons
19 | //
20 | // 2. The SECTION that use macro HEAPSORT to actually sort the vector
21 | //
22 | //--------------------------------------------------------------------------------------------------
23 | //
24 | // Define the comparison macro that is used by the HEAPSORT macro
25 | // This compares two 64 bits number passed in registers.
26 | //
27 | #MACRO
28 | //MACRO CompLong r1, r2, equalFlag, branchLabel, WReg[]
29 | if (equalFlag)
30 | \#Label BLE #r1, #r2, #branchLabel
31 | else
32 | \#Label BLT #r1, #r2, #branchLabel
33 | #END
34 | //
35 | // Actual code starts here
36 | //
37 | SETENV "RISCV", "RV64I:a,c,d,m,n,zicsr,zifencei", "LP64D", "linux"
Architecture is................................. RISCV
Number of registers............................. 32
Register bit length (XLEN)...................... 64
Number of floating registers.................... 32
Floating register bit length (FLEN)............. 64
(A) atomic extension............................ Used
(C) two byte opCode encoding extension.......... Used
(M) integer multiply/divide extension........... Used
(N) user level interrupt extension.............. Used
(ZTSO) total store ordering..................... Not Used
(ZICSR) control/status registers extension...... Used
(ZIFENCEI) instruction fetch fence extension.... Used
ABI............................................. LP64D
Operating System................................ LINUX
38 | // Define the srchitecture
[+][-] 39 | BaseDef // Include standard definitions
Macro [BASEDEF] source location is [JAR: /arch/RISCV/macros/BaseDef.mac]
[+][-] 39.1 |BASEDEF FrameWorkDef // Include DVASM framework base definitions
Macro [FRAMEWORKDEF] source location is [JAR: /framework/macros/FrameWorkDef.mac]
39.1.1 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 TRUE EQU 1
39.1.2 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 FALSE EQU 0
39.1.3 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 YES EQU 1
39.1.4 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 NO EQU 0
39.1.5 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF FLOFLOAT 3.14159265358 3.14159265358979323846264338327950288419717 PI EQU 3.14159265358979323846264338327950288419716939937510582097494459230781640628620899
39.1.6 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF FLOFLOAT 2.71828182845 2.71828182845904523536028747135266249775725 NAPIER EQU 2.71828182845904523536028747135266249775724709369995957496696762772407663035354759
39.1.6 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid section types
39.1.8 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_SHT_PROGBITS EQU 1
39.1.9 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000007 ELF_SHT_NOTE EQU 7
39.1.10 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000008 ELF_SHT_NOBITS EQU 8
39.1.10 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid section attributes
39.1.12 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_SHF_WRITE EQU 1
39.1.13 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_SHF_ALLOC EQU 2
39.1.14 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000004 ELF_SHF_EXECINSTR EQU 4
39.1.14 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid symbol bindings
39.1.16 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 ELF_STB_LOCAL EQU 0
39.1.17 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_STB_GLOBAL EQU 1
39.1.18 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_STB_WEAK EQU 2
39.1.18 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid symbol types
39.1.20 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 ELF_STT_NOTYPE EQU 0
39.1.21 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_STT_OBJECT EQU 1
39.1.22 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_STT_FUNC EQU 2
39.1.23 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000003 ELF_STT_SECTION EQU 3
39.1.24 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000004 ELF_STT_FILE EQU 4
39.2 |BASEDEF //
39.3 |BASEDEF // Base register definitions "R" prefix
39.4 |BASEDEF //
39.5 |BASEDEF ABSABSOLUTE 00000000 r0 EQU 0
39.6 |BASEDEF ABSABSOLUTE 00000001 r1 EQU 1
39.7 |BASEDEF ABSABSOLUTE 00000002 r2 EQU 2
39.8 |BASEDEF ABSABSOLUTE 00000003 r3 EQU 3
39.9 |BASEDEF ABSABSOLUTE 00000004 r4 EQU 4
39.10 |BASEDEF ABSABSOLUTE 00000005 r5 EQU 5
39.11 |BASEDEF ABSABSOLUTE 00000006 r6 EQU 6
39.12 |BASEDEF ABSABSOLUTE 00000007 r7 EQU 7
39.13 |BASEDEF ABSABSOLUTE 00000008 r8 EQU 8
39.14 |BASEDEF ABSABSOLUTE 00000009 r9 EQU 9
39.15 |BASEDEF ABSABSOLUTE 0000000A r10 EQU 10
39.16 |BASEDEF ABSABSOLUTE 0000000B r11 EQU 11
39.17 |BASEDEF ABSABSOLUTE 0000000C r12 EQU 12
39.18 |BASEDEF ABSABSOLUTE 0000000D r13 EQU 13
39.19 |BASEDEF ABSABSOLUTE 0000000E r14 EQU 14
39.20 |BASEDEF ABSABSOLUTE 0000000F r15 EQU 15
39.21 |BASEDEF ABSABSOLUTE 00000010 r16 EQU 16
39.22 |BASEDEF ABSABSOLUTE 00000011 r17 EQU 17
39.23 |BASEDEF ABSABSOLUTE 00000012 r18 EQU 18
39.24 |BASEDEF ABSABSOLUTE 00000013 r19 EQU 19
39.25 |BASEDEF ABSABSOLUTE 00000014 r20 EQU 20
39.26 |BASEDEF ABSABSOLUTE 00000015 r21 EQU 21
39.27 |BASEDEF ABSABSOLUTE 00000016 r22 EQU 22
39.28 |BASEDEF ABSABSOLUTE 00000017 r23 EQU 23
39.29 |BASEDEF ABSABSOLUTE 00000018 r24 EQU 24
39.30 |BASEDEF ABSABSOLUTE 00000019 r25 EQU 25
39.31 |BASEDEF ABSABSOLUTE 0000001A r26 EQU 26
39.32 |BASEDEF ABSABSOLUTE 0000001B r27 EQU 27
39.33 |BASEDEF ABSABSOLUTE 0000001C r28 EQU 28
39.34 |BASEDEF ABSABSOLUTE 0000001D r29 EQU 29
39.35 |BASEDEF ABSABSOLUTE 0000001E r30 EQU 30
39.36 |BASEDEF ABSABSOLUTE 0000001F r31 EQU 31
39.37 |BASEDEF //
39.38 |BASEDEF // Base register definitions "X" prefix
39.39 |BASEDEF //
39.40 |BASEDEF ABSABSOLUTE 00000000 x0 EQU 0
39.41 |BASEDEF ABSABSOLUTE 00000001 x1 EQU 1
39.42 |BASEDEF ABSABSOLUTE 00000002 x2 EQU 2
39.43 |BASEDEF ABSABSOLUTE 00000003 x3 EQU 3
39.44 |BASEDEF ABSABSOLUTE 00000004 x4 EQU 4
39.45 |BASEDEF ABSABSOLUTE 00000005 x5 EQU 5
39.46 |BASEDEF ABSABSOLUTE 00000006 x6 EQU 6
39.47 |BASEDEF ABSABSOLUTE 00000007 x7 EQU 7
39.48 |BASEDEF ABSABSOLUTE 00000008 x8 EQU 8
39.49 |BASEDEF ABSABSOLUTE 00000009 x9 EQU 9
39.50 |BASEDEF ABSABSOLUTE 0000000A x10 EQU 10
39.51 |BASEDEF ABSABSOLUTE 0000000B x11 EQU 11
39.52 |BASEDEF ABSABSOLUTE 0000000C x12 EQU 12
39.53 |BASEDEF ABSABSOLUTE 0000000D x13 EQU 13
39.54 |BASEDEF ABSABSOLUTE 0000000E x14 EQU 14
39.55 |BASEDEF ABSABSOLUTE 0000000F x15 EQU 15
39.56 |BASEDEF ABSABSOLUTE 00000010 x16 EQU 16
39.57 |BASEDEF ABSABSOLUTE 00000011 x17 EQU 17
39.58 |BASEDEF ABSABSOLUTE 00000012 x18 EQU 18
39.59 |BASEDEF ABSABSOLUTE 00000013 x19 EQU 19
39.60 |BASEDEF ABSABSOLUTE 00000014 x20 EQU 20
39.61 |BASEDEF ABSABSOLUTE 00000015 x21 EQU 21
39.62 |BASEDEF ABSABSOLUTE 00000016 x22 EQU 22
39.63 |BASEDEF ABSABSOLUTE 00000017 x23 EQU 23
39.64 |BASEDEF ABSABSOLUTE 00000018 x24 EQU 24
39.65 |BASEDEF ABSABSOLUTE 00000019 x25 EQU 25
39.66 |BASEDEF ABSABSOLUTE 0000001A x26 EQU 26
39.67 |BASEDEF ABSABSOLUTE 0000001B x27 EQU 27
39.68 |BASEDEF ABSABSOLUTE 0000001C x28 EQU 28
39.69 |BASEDEF ABSABSOLUTE 0000001D x29 EQU 29
39.70 |BASEDEF ABSABSOLUTE 0000001E x30 EQU 30
39.71 |BASEDEF ABSABSOLUTE 0000001F x31 EQU 31
39.72 |BASEDEF //
39.73 |BASEDEF // Alternate ABI register definitions
39.74 |BASEDEF //
39.75 |BASEDEF ABSABSOLUTE 00000001 ra EQU 1
39.76 |BASEDEF ABSABSOLUTE 00000002 sp EQU 2
39.77 |BASEDEF ABSABSOLUTE 00000003 gp EQU 3
39.78 |BASEDEF ABSABSOLUTE 00000004 tp EQU 4
39.79 |BASEDEF ABSABSOLUTE 00000005 t0 EQU 5
39.80 |BASEDEF ABSABSOLUTE 00000006 t1 EQU 6
39.81 |BASEDEF ABSABSOLUTE 00000007 t2 EQU 7
39.82 |BASEDEF ABSABSOLUTE 00000008 s0 EQU 8
39.83 |BASEDEF ABSABSOLUTE 00000009 s1 EQU 9
39.84 |BASEDEF ABSABSOLUTE 0000000A a0 EQU 10
39.85 |BASEDEF ABSABSOLUTE 0000000B a1 EQU 11
39.86 |BASEDEF ABSABSOLUTE 0000000C a2 EQU 12
39.87 |BASEDEF ABSABSOLUTE 0000000D a3 EQU 13
39.88 |BASEDEF ABSABSOLUTE 0000000E a4 EQU 14
39.89 |BASEDEF ABSABSOLUTE 0000000F a5 EQU 15
39.90 |BASEDEF ABSABSOLUTE 00000010 a6 EQU 16
39.91 |BASEDEF ABSABSOLUTE 00000011 a7 EQU 17
39.92 |BASEDEF ABSABSOLUTE 00000012 s2 EQU 18
39.93 |BASEDEF ABSABSOLUTE 00000013 s3 EQU 19
39.94 |BASEDEF ABSABSOLUTE 00000014 s4 EQU 20
39.95 |BASEDEF ABSABSOLUTE 00000015 s5 EQU 21
39.96 |BASEDEF ABSABSOLUTE 00000016 s6 EQU 22
39.97 |BASEDEF ABSABSOLUTE 00000017 s7 EQU 23
39.98 |BASEDEF ABSABSOLUTE 00000018 s8 EQU 24
39.99 |BASEDEF ABSABSOLUTE 00000019 s9 EQU 25
39.100 |BASEDEF ABSABSOLUTE 0000001A s10 EQU 26
39.101 |BASEDEF ABSABSOLUTE 0000001B s11 EQU 27
39.102 |BASEDEF ABSABSOLUTE 0000001C t3 EQU 28
39.103 |BASEDEF ABSABSOLUTE 0000001D t4 EQU 29
39.104 |BASEDEF ABSABSOLUTE 0000001E t5 EQU 30
39.105 |BASEDEF ABSABSOLUTE 0000001F t6 EQU 31
39.106 |BASEDEF //
39.107 |BASEDEF // Floating register definitions
39.108 |BASEDEF //
39.109 |BASEDEF ABSABSOLUTE 00000000 f0 EQU 0
39.110 |BASEDEF ABSABSOLUTE 00000001 f1 EQU 1
39.111 |BASEDEF ABSABSOLUTE 00000002 f2 EQU 2
39.112 |BASEDEF ABSABSOLUTE 00000003 f3 EQU 3
39.113 |BASEDEF ABSABSOLUTE 00000004 f4 EQU 4
39.114 |BASEDEF ABSABSOLUTE 00000005 f5 EQU 5
39.115 |BASEDEF ABSABSOLUTE 00000006 f6 EQU 6
39.116 |BASEDEF ABSABSOLUTE 00000007 f7 EQU 7
39.117 |BASEDEF ABSABSOLUTE 00000008 f8 EQU 8
39.118 |BASEDEF ABSABSOLUTE 00000009 f9 EQU 9
39.119 |BASEDEF ABSABSOLUTE 0000000A f10 EQU 10
39.120 |BASEDEF ABSABSOLUTE 0000000B f11 EQU 11
39.121 |BASEDEF ABSABSOLUTE 0000000C f12 EQU 12
39.122 |BASEDEF ABSABSOLUTE 0000000D f13 EQU 13
39.123 |BASEDEF ABSABSOLUTE 0000000E f14 EQU 14
39.124 |BASEDEF ABSABSOLUTE 0000000F f15 EQU 15
39.125 |BASEDEF ABSABSOLUTE 00000010 f16 EQU 16
39.126 |BASEDEF ABSABSOLUTE 00000011 f17 EQU 17
39.127 |BASEDEF ABSABSOLUTE 00000012 f18 EQU 18
39.128 |BASEDEF ABSABSOLUTE 00000013 f19 EQU 19
39.129 |BASEDEF ABSABSOLUTE 00000014 f20 EQU 20
39.130 |BASEDEF ABSABSOLUTE 00000015 f21 EQU 21
39.131 |BASEDEF ABSABSOLUTE 00000016 f22 EQU 22
39.132 |BASEDEF ABSABSOLUTE 00000017 f23 EQU 23
39.133 |BASEDEF ABSABSOLUTE 00000018 f24 EQU 24
39.134 |BASEDEF ABSABSOLUTE 00000019 f25 EQU 25
39.135 |BASEDEF ABSABSOLUTE 0000001A f26 EQU 26
39.136 |BASEDEF ABSABSOLUTE 0000001B f27 EQU 27
39.137 |BASEDEF ABSABSOLUTE 0000001C f28 EQU 28
39.138 |BASEDEF ABSABSOLUTE 0000001D f29 EQU 29
39.139 |BASEDEF ABSABSOLUTE 0000001E f30 EQU 30
39.140 |BASEDEF ABSABSOLUTE 0000001F f31 EQU 31
39.141 |BASEDEF //
39.142 |BASEDEF // Alternate ABI floating register definitions
39.143 |BASEDEF //
39.144 |BASEDEF ABSABSOLUTE 00000000 ft0 EQU 0
39.145 |BASEDEF ABSABSOLUTE 00000001 ft1 EQU 1
39.146 |BASEDEF ABSABSOLUTE 00000002 ft2 EQU 2
39.147 |BASEDEF ABSABSOLUTE 00000003 ft3 EQU 3
39.148 |BASEDEF ABSABSOLUTE 00000004 ft4 EQU 4
39.149 |BASEDEF ABSABSOLUTE 00000005 ft5 EQU 5
39.150 |BASEDEF ABSABSOLUTE 00000006 ft6 EQU 6
39.151 |BASEDEF ABSABSOLUTE 00000007 ft7 EQU 7
39.152 |BASEDEF ABSABSOLUTE 00000008 fs0 EQU 8
39.153 |BASEDEF ABSABSOLUTE 00000009 fs1 EQU 9
39.154 |BASEDEF ABSABSOLUTE 0000000A fa0 EQU 10
39.155 |BASEDEF ABSABSOLUTE 0000000B fa1 EQU 11
39.156 |BASEDEF ABSABSOLUTE 0000000C fa2 EQU 12
39.157 |BASEDEF ABSABSOLUTE 0000000D fa3 EQU 13
39.158 |BASEDEF ABSABSOLUTE 0000000E fa4 EQU 14
39.159 |BASEDEF ABSABSOLUTE 0000000F fa5 EQU 15
39.160 |BASEDEF ABSABSOLUTE 00000010 fa6 EQU 16
39.161 |BASEDEF ABSABSOLUTE 00000011 fa7 EQU 17
39.162 |BASEDEF ABSABSOLUTE 00000012 fs2 EQU 18
39.163 |BASEDEF ABSABSOLUTE 00000013 fs3 EQU 19
39.164 |BASEDEF ABSABSOLUTE 00000014 fs4 EQU 20
39.165 |BASEDEF ABSABSOLUTE 00000015 fs5 EQU 21
39.166 |BASEDEF ABSABSOLUTE 00000016 fs6 EQU 22
39.167 |BASEDEF ABSABSOLUTE 00000017 fs7 EQU 23
39.168 |BASEDEF ABSABSOLUTE 00000018 fs8 EQU 24
39.169 |BASEDEF ABSABSOLUTE 00000019 fs9 EQU 25
39.170 |BASEDEF ABSABSOLUTE 0000001A fs10 EQU 26
39.171 |BASEDEF ABSABSOLUTE 0000001B fs11 EQU 27
39.172 |BASEDEF ABSABSOLUTE 0000001C ft8 EQU 28
39.173 |BASEDEF ABSABSOLUTE 0000001D ft9 EQU 29
39.174 |BASEDEF ABSABSOLUTE 0000001E ft10 EQU 30
39.175 |BASEDEF ABSABSOLUTE 0000001F ft11 EQU 31
39.176 |BASEDEF //
39.177 |BASEDEF // Define Round Methods for Floating Point Arithmetic
39.178 |BASEDEF //
39.179 |BASEDEF ABSABSOLUTE 00000000 rm_rne EQU 0
39.180 |BASEDEF ABSABSOLUTE 00000001 rm_rtz EQU 1
39.181 |BASEDEF ABSABSOLUTE 00000002 rm_rdn EQU 2
39.182 |BASEDEF ABSABSOLUTE 00000003 rm_rup EQU 3
39.183 |BASEDEF ABSABSOLUTE 00000004 rm_rmm EQU 4
39.184 |BASEDEF ABSABSOLUTE 00000007 rm_dyn EQU 7
39.185 |BASEDEF //
39.186 |BASEDEF // Control registers
39.187 |BASEDEF //
39.188 |BASEDEF ABSABSOLUTE 00000001 fflags EQU 0x001
39.189 |BASEDEF ABSABSOLUTE 00000002 frm EQU 0x002
39.190 |BASEDEF ABSABSOLUTE 00000003 fcsr EQU 0x003
39.191 |BASEDEF ABSABSOLUTE 00000C00 cycle EQU 0xC00
39.192 |BASEDEF ABSABSOLUTE 00000C01 time EQU 0xC01
39.193 |BASEDEF ABSABSOLUTE 00000C02 instret EQU 0xC02
39.194 |BASEDEF ABSABSOLUTE 00000C80 cycleh EQU 0xC80
39.195 |BASEDEF ABSABSOLUTE 00000C81 timeh EQU 0xC81
39.196 |BASEDEF ABSABSOLUTE 00000C82 instreth EQU 0xC82
40 | //
[+][-] 41 | Code TextSect // Start .text section
Macro [TEXTSECT] source location is [JAR: /framework/macros/TextSect.mac]
41.1 |TEXTSECT 000000 Code SECTION ELF_SHT_PROGBITS,ELF_SHF_ALLOC+ELF_SHF_EXECINSTR,8,".text" // Text section definition
42 | C.SUSPEND // Do not use two byte opCode extension
Use of C extension has been suspended
43 | //
[+][-] 44 | dvasmsortlong /> Entry label
Macro [ENTRY] source location is [JAR: /arch/RISCV/macros/Entry.mac]
45 | ENTRY Stack=!"" // Leaf entry, only A* and T* registers
45.1 |ENTRY EXPORT dvasmsortlong
45.2 |ENTRY 000000 dvasmsortlong DWRD 0[0]
ABSOLUTE, alignment [8], length [8], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 0000000000000000
Code [BIG ENDIAN] -> 0000000000000000
Code [DECIMAL ] -> 0
46 | // are used. No need to use a stack
47 | // or save/restore registers
[+][-] 48 | HEAPSORT a0, a1, 64, CompLong, [t0-6, a2-3] // Invoke HEAPSORT macro
Macro [HEAPSORT] source location is [JAR: /arch/RISCV/macros/HeapSort.mac]
48.1 |HEAPSORT //
48.2 |HEAPSORT // Registers used by macro by default or as specified by user
48.3 |HEAPSORT //
48.4 |HEAPSORT // a0 - address of buffer
48.5 |HEAPSORT // a1 - number of records in buffer
48.6 |HEAPSORT //
48.7 |HEAPSORT // t0 - end address of buffer
48.8 |HEAPSORT // t1 - end address of record being sorted
48.9 |HEAPSORT // t2 - content of record being sorted
48.10 |HEAPSORT // t3 - end offset of record being sorted
48.11 |HEAPSORT // t4 - end address of parent record when adjusting heap
48.12 |HEAPSORT // t5 - end offset of parent left child
48.13 |HEAPSORT // t6 - end address of parent left child
48.14 |HEAPSORT // a2 - content of parent left child
48.15 |HEAPSORT // a3 - content of parent right child
48.16 |HEAPSORT //
48.17 |HEAPSORT // Code to create the heap
48.18 |HEAPSORT //
48.19 |HEAPSORT 000000 139E3500 SLLI t3, 3[a1] // Get buffer Size
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 00359E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 11
Shift Amount.............. +03 [HEX]
Shift Amount Encoded...... 000011 [BIN] Bits [6:0]
48.20 |HEAPSORT 000004 B302AE00 ADD t0, t3, a0 // Get last record end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AE02B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 10
Source 1 Register...... 28
48.21 |HEAPSORT 000008 135E1E00 SRLI t3, 1 // Get mid-record end offset
SRLI: Shift Logical Right Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001E5E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 28
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.22 |HEAPSORT 00000C 3303AE00 ADD t1, t3, a0 // Get mid-record end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AE0333 [BIG ENDIAN]
Destination Register...... 6
Source 2 Register...... 10
Source 1 Register...... 28
[+][-] 48.23 |HEAPSORT WHILE Condition= ( t1 > a0 ), /> Start heap build main loop
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
48.24 |HEAPSORT RepeatCode= [!"ADDI t1, -8", />
48.25 |HEAPSORT !"ADDI t3, -8"]
48.25.1 |HEAPSORT:WHILE 000010 Asm000005 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 48.25.2 |HEAPSORT:WHILE __CondGen ( t1 > a0 ), true, Asm000006, Asm000007, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.25.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BLE t1, a0, Asm000007
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.25.2.1.1 LE:__CONDGEN:BLE|HEAPSORT:WHILE:__CONDGEN:BLE 000010 63566506 BGE a0, t1, Asm000007
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 06655663 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 6
Immediate PCRel........... 06C [HEX]
Immediate Sect. Offset.... 0000007C [HEX]
Immediate Bits [12:1]..... 0_0_000011_0110 [BIN] bits [12:1]
48.25.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 000014 Asm000006 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.25.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
48.26 |HEAPSORT 000014 833383FF LD t2, -8[t1] // Load record
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... FF833383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 6
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 48.27 |HEAPSORT MV t4, t1 // Copy rec addr as parent addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
48.27.1 |HEAPSORT:MV 000018 930E0300 ADDI t4, 0[t1]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00030E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
48.28 |HEAPSORT 00001C 131F1E00 SLLI t5, 1[t3] // Get child end offset
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001E1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.29 |HEAPSORT 000020 B30FAF00 ADD t6, t5, a0 // Get child end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 48.30 |HEAPSORT WHILE Condition= ( t6 <= t0 ), /> Get child end addr
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
48.31 |HEAPSORT RepeatCode= [!"SLLI t5, 1", /> Get new child offset
48.32 |HEAPSORT !"ADD t6, t5, a0"] // Get new child addr
48.32.1 |HEAPSORT:WHILE 000024 Asm000008 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 48.32.2 |HEAPSORT:WHILE __CondGen ( t6 <= t0 ), true, Asm000009, Asm000010, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.32.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BGT t6, t0, Asm000010
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
48.32.2.1.1 LE:__CONDGEN:BGT|HEAPSORT:WHILE:__CONDGEN:BGT 000024 63C4F205 BLT t0, t6, Asm000010
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 05F2C463 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... 048 [HEX]
Immediate Sect. Offset.... 0000006C [HEX]
Immediate Bits [12:1]..... 0_0_000010_0100 [BIN] bits [12:1]
48.32.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 000028 Asm000009 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.32.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
48.33 |HEAPSORT 000028 03B68FFF LD a2, -8[t6] // Load child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... FF8FB603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 31
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 48.34 |HEAPSORT IF ( t6 >= t0 ), GOTO, Id= Asm000001 // Check if next child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 48.34.1 |HEAPSORT:IF __CondGen ( t6 >= t0 ), false, Asm000001, Asm000011, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
48.34.1.1 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 00002C 63D45F02 BGE t6, t0, Asm000001
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 025FD463 [BIG ENDIAN]
Source 1 Register...... 31
Source 2 Register...... 5
Immediate PCRel........... 028 [HEX]
Immediate Sect. Offset.... 00000054 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0100 [BIN] bits [12:1]
48.34.1.2 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 000030 Asm000011 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.35 |HEAPSORT 000030 83B60F00 LD a3, 0[t6] // Load child next
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000FB683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 48.36 |HEAPSORT CompLong a3, a2, false, Asm000001, [] // Check which child is max
Macro [COMPLONG] source location is [Inline macro from line 27 to line 33 included]
[+][-] 48.36.1 EAPSORT:COMPLONG|HEAPSORT:COMPLONG BLE a3, a2, Asm000001
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.36.1.1 ORT:COMPLONG:BLE|HEAPSORT:COMPLONG:BLE 000034 6350D602 BGE a2, a3, Asm000001
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 02D65063 [BIG ENDIAN]
Source 1 Register...... 12
Source 2 Register...... 13
Immediate PCRel........... 020 [HEX]
Immediate Sect. Offset.... 00000054 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0000 [BIN] bits [12:1]
48.37 |HEAPSORT
[+][-] 48.38 |HEAPSORT CompLong a3, t2, true, Asm000002, [] // Check if rec is max
Macro [COMPLONG] source location is [Inline macro from line 27 to line 33 included]
[+][-] 48.38.1 EAPSORT:COMPLONG|HEAPSORT:COMPLONG BLE a3, t2, Asm000002
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.38.1.1 ORT:COMPLONG:BLE|HEAPSORT:COMPLONG:BLE 000038 63DAD302 BGE t2, a3, Asm000002
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 02D3DA63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 13
Immediate PCRel........... 034 [HEX]
Immediate Sect. Offset.... 0000006C [HEX]
Immediate Bits [12:1]..... 0_0_000001_1010 [BIN] bits [12:1]
48.39 |HEAPSORT 00003C 23BCDEFE SD a3, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FEDEBC23 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
48.40 |HEAPSORT 000040 938E8F00 ADDI t4, 8[t6] // Next child become parent
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
48.41 |HEAPSORT 000044 130F8F00 ADDI t5, 8 // Get next child offset
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F0F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 48.42 |HEAPSORT CONTINUE
Macro [CONTINUE] source location is [JAR: /arch/RISCV/macros/Continue.mac]
48.42.1 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000048 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.42.2 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 00004C B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
48.42.3 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000050 6FF05FFD JAL Asm000008
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FD5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00002C [HEX]
Immediate Sect. Offset.... 00000024 [HEX]
Immediate Encoded......... 1_11111111_1_1111101010 [BIN] Bits [20:1]
[+][-] 48.43 |HEAPSORT Asm000001 CompLong a2, t2, true, Asm000002, [] // Check child with rec
Macro [COMPLONG] source location is [Inline macro from line 27 to line 33 included]
[+][-] 48.43.1 EAPSORT:COMPLONG|HEAPSORT:COMPLONG Asm000001 BLE a2, t2, Asm000002
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.43.1.1 ORT:COMPLONG:BLE|HEAPSORT:COMPLONG:BLE 000054 63DCC300 Asm000001 BGE t2, a2, Asm000002
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 00C3DC63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 12
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 0000006C [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
48.44 |HEAPSORT 000058 23BCCEFE SD a2, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FECEBC23 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 48.45 |HEAPSORT MV t4, t6 // Child become parent
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
48.45.1 |HEAPSORT:MV 00005C 938E0F00 ADDI t4, 0[t6]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 48.46 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
48.46.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 000060 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.46.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 000064 B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 48.46.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t6 <= t0 ), false, Asm000009, Asm000010, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.46.3.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BLE t6, t0, Asm000009
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.46.3.1.1 LE:__CONDGEN:BLE|HEAPSORT:ENDWHILE:__CONDGEN:BLE 000068 E3D0F2FD BGE t0, t6, Asm000009
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... FDF2D0E3 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... -40 [HEX]
Immediate Sect. Offset.... 00000028 [HEX]
Immediate Bits [12:1]..... 1_1_111110_0000 [BIN] bits [12:1]
48.46.3.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 00006C Asm000010 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.46.4 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
48.47 |HEAPSORT 00006C 23BC7EFE Asm000002 SD t2, -8[t4]
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FE7EBC23 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 48.48 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
48.48.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 000070 130383FF ADDI t1, -8
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF830313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 6
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
48.48.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 000074 130E8EFF ADDI t3, -8
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF8E0E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 28
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 48.48.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t1 > a0 ), false, Asm000006, Asm000007, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.48.3.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BGT t1, a0, Asm000006
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
48.48.3.1.1 LE:__CONDGEN:BGT|HEAPSORT:ENDWHILE:__CONDGEN:BGT 000078 E34E65F8 BLT a0, t1, Asm000006
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... F8654EE3 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 6
Immediate PCRel........... -64 [HEX]
Immediate Sect. Offset.... 00000014 [HEX]
Immediate Bits [12:1]..... 1_1_111100_1110 [BIN] bits [12:1]
48.48.3.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 00007C Asm000007 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.48.4 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
48.49 |HEAPSORT //
48.50 |HEAPSORT // Code to sort
48.51 |HEAPSORT //
48.52 |HEAPSORT 00007C 938282FF ADDI t0, -8 // Reduce heap Size by one
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF828293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 48.53 |HEAPSORT WHILE Condition= ( t0 > a0 ), /> Start sort main loop
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
48.54 |HEAPSORT RepeatCode= [!"ADDI t0,-8"]
48.54.1 |HEAPSORT:WHILE 000080 Asm000012 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 48.54.2 |HEAPSORT:WHILE __CondGen ( t0 > a0 ), true, Asm000013, Asm000014, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.54.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BLE t0, a0, Asm000014
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.54.2.1.1 LE:__CONDGEN:BLE|HEAPSORT:WHILE:__CONDGEN:BLE 000080 635C5506 BGE a0, t0, Asm000014
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 06555C63 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 5
Immediate PCRel........... 078 [HEX]
Immediate Sect. Offset.... 000000F8 [HEX]
Immediate Bits [12:1]..... 0_0_000011_1100 [BIN] bits [12:1]
48.54.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 000084 Asm000013 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.54.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
48.55 |HEAPSORT 000084 130E8000 ADDI t3, 8[0] // Get starting record end offset
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00800E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 0
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
48.56 |HEAPSORT 000088 13038500 ADDI t1, 8[a0] // Get starting record end addr
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00850313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 10
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
48.57 |HEAPSORT 00008C 83B30200 LD t2, 0[t0] // Load record
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0002B383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 5
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
48.58 |HEAPSORT 000090 03360500 LD a2, 0[a0] // Get firt record in heap - last in sort order
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00053603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 10
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
48.59 |HEAPSORT 000094 23B0C200 SD a2, 0[t0] // Store at the end of the heap
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C2B023 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 5
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 48.60 |HEAPSORT MV t4, t1 // Copy rec addr as parent addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
48.60.1 |HEAPSORT:MV 000098 930E0300 ADDI t4, 0[t1]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00030E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
48.61 |HEAPSORT 00009C 131F1E00 SLLI t5, 1[t3] // Get child end offset
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001E1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.62 |HEAPSORT 0000A0 B30FAF00 ADD t6, t5, a0 // Get child end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 48.63 |HEAPSORT WHILE Condition= ( t6 <= t0 ), /> Get child end addr
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
48.64 |HEAPSORT RepeatCode= [!"SLLI t5, 1", /> Get new child offset
48.65 |HEAPSORT !"ADD t6, t5, a0"] // Get new child addr
48.65.1 |HEAPSORT:WHILE 0000A4 Asm000015 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 48.65.2 |HEAPSORT:WHILE __CondGen ( t6 <= t0 ), true, Asm000016, Asm000017, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.65.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BGT t6, t0, Asm000017
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
48.65.2.1.1 LE:__CONDGEN:BGT|HEAPSORT:WHILE:__CONDGEN:BGT 0000A4 63C4F205 BLT t0, t6, Asm000017
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 05F2C463 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... 048 [HEX]
Immediate Sect. Offset.... 000000EC [HEX]
Immediate Bits [12:1]..... 0_0_000010_0100 [BIN] bits [12:1]
48.65.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 0000A8 Asm000016 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.65.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
48.66 |HEAPSORT 0000A8 03B68FFF LD a2, -8[t6] // Load child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... FF8FB603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 31
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 48.67 |HEAPSORT IF ( t6 >= t0 ), GOTO, Id= Asm000003 // Check if next child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 48.67.1 |HEAPSORT:IF __CondGen ( t6 >= t0 ), false, Asm000003, Asm000018, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
48.67.1.1 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 0000AC 63D45F02 BGE t6, t0, Asm000003
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 025FD463 [BIG ENDIAN]
Source 1 Register...... 31
Source 2 Register...... 5
Immediate PCRel........... 028 [HEX]
Immediate Sect. Offset.... 000000D4 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0100 [BIN] bits [12:1]
48.67.1.2 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 0000B0 Asm000018 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.68 |HEAPSORT 0000B0 83B60F00 LD a3, 0[t6] // Load child next
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000FB683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 48.69 |HEAPSORT CompLong a3, a2, false, Asm000003, [] // Check which child is max
Macro [COMPLONG] source location is [Inline macro from line 27 to line 33 included]
[+][-] 48.69.1 EAPSORT:COMPLONG|HEAPSORT:COMPLONG BLE a3, a2, Asm000003
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.69.1.1 ORT:COMPLONG:BLE|HEAPSORT:COMPLONG:BLE 0000B4 6350D602 BGE a2, a3, Asm000003
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 02D65063 [BIG ENDIAN]
Source 1 Register...... 12
Source 2 Register...... 13
Immediate PCRel........... 020 [HEX]
Immediate Sect. Offset.... 000000D4 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0000 [BIN] bits [12:1]
[+][-] 48.70 |HEAPSORT CompLong a3, t2, true, Asm000004, [] // Check if rec is max
Macro [COMPLONG] source location is [Inline macro from line 27 to line 33 included]
[+][-] 48.70.1 EAPSORT:COMPLONG|HEAPSORT:COMPLONG BLE a3, t2, Asm000004
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.70.1.1 ORT:COMPLONG:BLE|HEAPSORT:COMPLONG:BLE 0000B8 63DAD302 BGE t2, a3, Asm000004
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 02D3DA63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 13
Immediate PCRel........... 034 [HEX]
Immediate Sect. Offset.... 000000EC [HEX]
Immediate Bits [12:1]..... 0_0_000001_1010 [BIN] bits [12:1]
48.71 |HEAPSORT 0000BC 23BCDEFE SD a3, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FEDEBC23 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
48.72 |HEAPSORT 0000C0 938E8F00 ADDI t4, 8[t6] // Next child become parent
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
48.73 |HEAPSORT 0000C4 130F8F00 ADDI t5, 8 // Get next child offset
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F0F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 48.74 |HEAPSORT CONTINUE
Macro [CONTINUE] source location is [JAR: /arch/RISCV/macros/Continue.mac]
48.74.1 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 0000C8 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.74.2 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 0000CC B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
48.74.3 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 0000D0 6FF05FFD JAL Asm000015
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FD5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00002C [HEX]
Immediate Sect. Offset.... 000000A4 [HEX]
Immediate Encoded......... 1_11111111_1_1111101010 [BIN] Bits [20:1]
[+][-] 48.75 |HEAPSORT Asm000003 CompLong a2, t2, true, Asm000004, [] // Check child with rec
Macro [COMPLONG] source location is [Inline macro from line 27 to line 33 included]
[+][-] 48.75.1 EAPSORT:COMPLONG|HEAPSORT:COMPLONG Asm000003 BLE a2, t2, Asm000004
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.75.1.1 ORT:COMPLONG:BLE|HEAPSORT:COMPLONG:BLE 0000D4 63DCC300 Asm000003 BGE t2, a2, Asm000004
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 00C3DC63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 12
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 000000EC [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
48.76 |HEAPSORT 0000D8 23BCCEFE SD a2, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FECEBC23 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 48.77 |HEAPSORT MV t4, t6 // Child become parent
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
48.77.1 |HEAPSORT:MV 0000DC 938E0F00 ADDI t4, 0[t6]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 48.78 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
48.78.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000E0 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
48.78.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000E4 B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 48.78.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t6 <= t0 ), false, Asm000016, Asm000017, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.78.3.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BLE t6, t0, Asm000016
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
48.78.3.1.1 LE:__CONDGEN:BLE|HEAPSORT:ENDWHILE:__CONDGEN:BLE 0000E8 E3D0F2FD BGE t0, t6, Asm000016
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... FDF2D0E3 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... -40 [HEX]
Immediate Sect. Offset.... 000000A8 [HEX]
Immediate Bits [12:1]..... 1_1_111110_0000 [BIN] bits [12:1]
48.78.3.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 0000EC Asm000017 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.78.4 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
48.79 |HEAPSORT 0000EC 23BC7EFE Asm000004 SD t2, -8[t4] // Save record in current child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FE7EBC23 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 48.80 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
48.80.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000F0 938282FF ADDI t0,-8
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF828293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 48.80.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t0 > a0 ), false, Asm000013, Asm000014, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 48.80.2.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BGT t0, a0, Asm000013
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
48.80.2.1.1 LE:__CONDGEN:BGT|HEAPSORT:ENDWHILE:__CONDGEN:BGT 0000F4 E34855F8 BLT a0, t0, Asm000013
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... F85548E3 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 5
Immediate PCRel........... -70 [HEX]
Immediate Sect. Offset.... 00000084 [HEX]
Immediate Bits [12:1]..... 1_1_111100_1000 [BIN] bits [12:1]
48.80.2.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 0000F8 Asm000014 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
48.80.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 49 | Exit EXIT // Return to caller
Macro [EXIT] source location is [JAR: /arch/RISCV/macros/Exit.mac]
49.1 |EXIT 0000F8 Exit BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
49.2 |EXIT 0000F8 67800000 JALR 0, 0[ra] // Return to caller
JALR: Jump to ( Reg1 + immediate ) address, and store link address in RegD
Machine Instruction....... 00008067 [BIG ENDIAN]
Destination Register...... 0
Source 1 Register...... 1
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
50 | //
51 | END
Code SECTION 00008 000000FC .text PROGBITS ALLOC+EXECUTE
[+][-] A0 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 39.84
Referenced in Statement: 48.20
Referenced in Statement: 48.22
Referenced in Statement: 48.25.2.1.1
Referenced in Statement: 48.29
Referenced in Statement: 48.42.2
Referenced in Statement: 48.46.2
Referenced in Statement: 48.48.3.1.1
Referenced in Statement: 48.54.2.1.1
Referenced in Statement: 48.56
Referenced in Statement: 48.58
Referenced in Statement: 48.62
Referenced in Statement: 48.74.2
Referenced in Statement: 48.78.2
Referenced in Statement: 48.80.2.1.1
[+][-] A1 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 39.85
Referenced in Statement: 48.19
[+][-] A2 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 39.86
Referenced in Statement: 48.33
Referenced in Statement: 48.36.1.1
Referenced in Statement: 48.43.1.1
Referenced in Statement: 48.44
Referenced in Statement: 48.58
Referenced in Statement: 48.59
Referenced in Statement: 48.66
Referenced in Statement: 48.69.1.1
Referenced in Statement: 48.75.1.1
Referenced in Statement: 48.76
[+][-] A3 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 39.87
Referenced in Statement: 48.35
Referenced in Statement: 48.36.1.1
Referenced in Statement: 48.38.1.1
Referenced in Statement: 48.39
Referenced in Statement: 48.68
Referenced in Statement: 48.69.1.1
Referenced in Statement: 48.70.1.1
Referenced in Statement: 48.71
[+][-] A4 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 39.88
[+][-] A5 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 39.89
[+][-] A6 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 39.90
[+][-] A7 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 39.91
[+][-] ASM000001 OFFSET [Code] 00002 00004 00001 000004 00000054
Defined in Statement: 48.43.1.1
Referenced in Statement: 48.34.1.1
Referenced in Statement: 48.36.1.1
[+][-] ASM000002 OFFSET [Code] 00002 00004 00001 000004 0000006C
Defined in Statement: 48.47
Referenced in Statement: 48.38.1.1
Referenced in Statement: 48.43.1.1
[+][-] ASM000003 OFFSET [Code] 00002 00004 00001 000004 000000D4
Defined in Statement: 48.75.1.1
Referenced in Statement: 48.67.1.1
Referenced in Statement: 48.69.1.1
[+][-] ASM000004 OFFSET [Code] 00002 00004 00001 000004 000000EC
Defined in Statement: 48.79
Referenced in Statement: 48.70.1.1
Referenced in Statement: 48.75.1.1
[+][-] ASM000005 OFFSET [Code] 00001 00001 00000 000000 00000010
Defined in Statement: 48.25.1
[+][-] ASM000006 OFFSET [Code] 00001 00001 00000 000000 00000014
Defined in Statement: 48.25.2.2
Referenced in Statement: 48.48.3.1.1
[+][-] ASM000007 OFFSET [Code] 00001 00001 00000 000000 0000007C
Defined in Statement: 48.48.3.2
Referenced in Statement: 48.25.2.1.1
[+][-] ASM000008 OFFSET [Code] 00001 00001 00000 000000 00000024
Defined in Statement: 48.32.1
Referenced in Statement: 48.42.3
[+][-] ASM000009 OFFSET [Code] 00001 00001 00000 000000 00000028
Defined in Statement: 48.32.2.2
Referenced in Statement: 48.46.3.1.1
[+][-] ASM000010 OFFSET [Code] 00001 00001 00000 000000 0000006C
Defined in Statement: 48.46.3.2
Referenced in Statement: 48.32.2.1.1
[+][-] ASM000011 OFFSET [Code] 00001 00001 00000 000000 00000030
Defined in Statement: 48.34.1.2
[+][-] ASM000012 OFFSET [Code] 00001 00001 00000 000000 00000080
Defined in Statement: 48.54.1
[+][-] ASM000013 OFFSET [Code] 00001 00001 00000 000000 00000084
Defined in Statement: 48.54.2.2
Referenced in Statement: 48.80.2.1.1
[+][-] ASM000014 OFFSET [Code] 00001 00001 00000 000000 000000F8
Defined in Statement: 48.80.2.2
Referenced in Statement: 48.54.2.1.1
[+][-] ASM000015 OFFSET [Code] 00001 00001 00000 000000 000000A4
Defined in Statement: 48.65.1
Referenced in Statement: 48.74.3
[+][-] ASM000016 OFFSET [Code] 00001 00001 00000 000000 000000A8
Defined in Statement: 48.65.2.2
Referenced in Statement: 48.78.3.1.1
[+][-] ASM000017 OFFSET [Code] 00001 00001 00000 000000 000000EC
Defined in Statement: 48.78.3.2
Referenced in Statement: 48.65.2.1.1
[+][-] ASM000018 OFFSET [Code] 00001 00001 00000 000000 000000B0
Defined in Statement: 48.67.1.2
[+][-] CODE OFFSET [Code] 00001 00000 00001 000000 00000000
Defined in Statement: 41.1
[+][-] CYCLE ABSOLUTE 00001 00000 00001 000000 00000C00
Defined in Statement: 39.191
[+][-] CYCLEH ABSOLUTE 00001 00000 00001 000000 00000C80
Defined in Statement: 39.194
[+][-] DVASMSORTLONG dvasmsortlong OBJECT GLOBAL OFFSET [Code] 00008 00008 00000 000000 00000000
Defined in Statement: 45.2
Referenced in Statement: 45.1
[+][-] ELF_SHF_ALLOC ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.1.13
Referenced in Statement: 41.1
[+][-] ELF_SHF_EXECINSTR ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.1.14
Referenced in Statement: 41.1
[+][-] ELF_SHF_WRITE ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.1.12
[+][-] ELF_SHT_NOBITS ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 39.1.10
[+][-] ELF_SHT_NOTE ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.1.9
[+][-] ELF_SHT_PROGBITS ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.1.8
Referenced in Statement: 41.1
[+][-] ELF_STB_GLOBAL ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.1.17
[+][-] ELF_STB_LOCAL ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.1.16
[+][-] ELF_STB_WEAK ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.1.18
[+][-] ELF_STT_FILE ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.1.24
[+][-] ELF_STT_FUNC ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.1.22
[+][-] ELF_STT_NOTYPE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.1.20
[+][-] ELF_STT_OBJECT ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.1.21
[+][-] ELF_STT_SECTION ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.1.23
[+][-] EXIT OFFSET [Code] 00001 00001 00000 000000 000000F8
Defined in Statement: 49.1
[+][-] F0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.109
[+][-] F1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.110
[+][-] F10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 39.119
[+][-] F11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 39.120
[+][-] F12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 39.121
[+][-] F13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 39.122
[+][-] F14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 39.123
[+][-] F15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 39.124
[+][-] F16 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 39.125
[+][-] F17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 39.126
[+][-] F18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 39.127
[+][-] F19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 39.128
[+][-] F2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.111
[+][-] F20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 39.129
[+][-] F21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 39.130
[+][-] F22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 39.131
[+][-] F23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 39.132
[+][-] F24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 39.133
[+][-] F25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 39.134
[+][-] F26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 39.135
[+][-] F27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 39.136
[+][-] F28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 39.137
[+][-] F29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 39.138
[+][-] F3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.112
[+][-] F30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 39.139
[+][-] F31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 39.140
[+][-] F4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.113
[+][-] F5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 39.114
[+][-] F6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 39.115
[+][-] F7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.116
[+][-] F8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 39.117
[+][-] F9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 39.118
[+][-] FA0 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 39.154
[+][-] FA1 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 39.155
[+][-] FA2 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 39.156
[+][-] FA3 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 39.157
[+][-] FA4 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 39.158
[+][-] FA5 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 39.159
[+][-] FA6 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 39.160
[+][-] FA7 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 39.161
[+][-] FALSE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.1.2
[+][-] FCSR ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.190
[+][-] FFLAGS ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.188
[+][-] FRM ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.189
[+][-] FS0 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 39.152
[+][-] FS1 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 39.153
[+][-] FS10 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 39.170
[+][-] FS11 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 39.171
[+][-] FS2 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 39.162
[+][-] FS3 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 39.163
[+][-] FS4 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 39.164
[+][-] FS5 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 39.165
[+][-] FS6 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 39.166
[+][-] FS7 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 39.167
[+][-] FS8 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 39.168
[+][-] FS9 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 39.169
[+][-] FT0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.144
[+][-] FT1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.145
[+][-] FT10 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 39.174
[+][-] FT11 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 39.175
[+][-] FT2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.146
[+][-] FT3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.147
[+][-] FT4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.148
[+][-] FT5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 39.149
[+][-] FT6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 39.150
[+][-] FT7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.151
[+][-] FT8 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 39.172
[+][-] FT9 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 39.173
[+][-] GP ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.77
[+][-] INSTRET ABSOLUTE 00001 00000 00001 000000 00000C02
Defined in Statement: 39.193
[+][-] INSTRETH ABSOLUTE 00001 00000 00001 000000 00000C82
Defined in Statement: 39.196
[+][-] NAPIER FLOAT 00001 00000 00001 000000 2.71828182845904523536028747132.71828182845904523536028747135266249775725
Defined in Statement: 39.1.6
[+][-] NO ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.1.4
[+][-] PI FLOAT 00001 00000 00001 000000 3.14159265358979323846264338323.14159265358979323846264338327950288419717
Defined in Statement: 39.1.5
[+][-] R0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.5
[+][-] R1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.6
[+][-] R10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 39.15
[+][-] R11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 39.16
[+][-] R12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 39.17
[+][-] R13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 39.18
[+][-] R14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 39.19
[+][-] R15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 39.20
[+][-] R16 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 39.21
[+][-] R17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 39.22
[+][-] R18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 39.23
[+][-] R19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 39.24
[+][-] R2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.7
[+][-] R20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 39.25
[+][-] R21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 39.26
[+][-] R22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 39.27
[+][-] R23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 39.28
[+][-] R24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 39.29
[+][-] R25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 39.30
[+][-] R26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 39.31
[+][-] R27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 39.32
[+][-] R28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 39.33
[+][-] R29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 39.34
[+][-] R3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.8
[+][-] R30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 39.35
[+][-] R31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 39.36
[+][-] R4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.9
[+][-] R5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 39.10
[+][-] R6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 39.11
[+][-] R7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.12
[+][-] R8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 39.13
[+][-] R9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 39.14
[+][-] RA ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.75
Referenced in Statement: 49.2
[+][-] RM_DYN ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.184
[+][-] RM_RDN ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.181
[+][-] RM_RMM ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.183
[+][-] RM_RNE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.179
[+][-] RM_RTZ ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.180
[+][-] RM_RUP ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.182
[+][-] S0 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 39.82
[+][-] S1 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 39.83
[+][-] S10 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 39.100
[+][-] S11 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 39.101
[+][-] S2 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 39.92
[+][-] S3 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 39.93
[+][-] S4 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 39.94
[+][-] S5 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 39.95
[+][-] S6 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 39.96
[+][-] S7 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 39.97
[+][-] S8 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 39.98
[+][-] S9 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 39.99
[+][-] SP ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.76
[+][-] T0 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 39.79
Referenced in Statement: 48.20
Referenced in Statement: 48.32.2.1.1
Referenced in Statement: 48.34.1.1
Referenced in Statement: 48.46.3.1.1
Referenced in Statement: 48.52
Referenced in Statement: 48.54.2.1.1
Referenced in Statement: 48.57
Referenced in Statement: 48.59
Referenced in Statement: 48.65.2.1.1
Referenced in Statement: 48.67.1.1
Referenced in Statement: 48.78.3.1.1
Referenced in Statement: 48.80.1
Referenced in Statement: 48.80.2.1.1
[+][-] T1 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 39.80
Referenced in Statement: 48.22
Referenced in Statement: 48.25.2.1.1
Referenced in Statement: 48.26
Referenced in Statement: 48.27.1
Referenced in Statement: 48.48.1
Referenced in Statement: 48.48.3.1.1
Referenced in Statement: 48.56
Referenced in Statement: 48.60.1
[+][-] T2 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.81
Referenced in Statement: 48.26
Referenced in Statement: 48.38.1.1
Referenced in Statement: 48.43.1.1
Referenced in Statement: 48.47
Referenced in Statement: 48.57
Referenced in Statement: 48.70.1.1
Referenced in Statement: 48.75.1.1
Referenced in Statement: 48.79
[+][-] T3 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 39.102
Referenced in Statement: 48.19
Referenced in Statement: 48.20
Referenced in Statement: 48.21
Referenced in Statement: 48.22
Referenced in Statement: 48.28
Referenced in Statement: 48.48.2
Referenced in Statement: 48.55
Referenced in Statement: 48.61
[+][-] T4 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 39.103
Referenced in Statement: 48.27.1
Referenced in Statement: 48.39
Referenced in Statement: 48.40
Referenced in Statement: 48.44
Referenced in Statement: 48.45.1
Referenced in Statement: 48.47
Referenced in Statement: 48.60.1
Referenced in Statement: 48.71
Referenced in Statement: 48.72
Referenced in Statement: 48.76
Referenced in Statement: 48.77.1
Referenced in Statement: 48.79
[+][-] T5 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 39.104
Referenced in Statement: 48.28
Referenced in Statement: 48.29
Referenced in Statement: 48.41
Referenced in Statement: 48.42.1
Referenced in Statement: 48.42.2
Referenced in Statement: 48.46.1
Referenced in Statement: 48.46.2
Referenced in Statement: 48.61
Referenced in Statement: 48.62
Referenced in Statement: 48.73
Referenced in Statement: 48.74.1
Referenced in Statement: 48.74.2
Referenced in Statement: 48.78.1
Referenced in Statement: 48.78.2
[+][-] T6 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 39.105
Referenced in Statement: 48.29
Referenced in Statement: 48.32.2.1.1
Referenced in Statement: 48.33
Referenced in Statement: 48.34.1.1
Referenced in Statement: 48.35
Referenced in Statement: 48.40
Referenced in Statement: 48.42.2
Referenced in Statement: 48.45.1
Referenced in Statement: 48.46.2
Referenced in Statement: 48.46.3.1.1
Referenced in Statement: 48.62
Referenced in Statement: 48.65.2.1.1
Referenced in Statement: 48.66
Referenced in Statement: 48.67.1.1
Referenced in Statement: 48.68
Referenced in Statement: 48.72
Referenced in Statement: 48.74.2
Referenced in Statement: 48.77.1
Referenced in Statement: 48.78.2
Referenced in Statement: 48.78.3.1.1
[+][-] TIME ABSOLUTE 00001 00000 00001 000000 00000C01
Defined in Statement: 39.192
[+][-] TIMEH ABSOLUTE 00001 00000 00001 000000 00000C81
Defined in Statement: 39.195
[+][-] TP ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.78
[+][-] TRUE ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.1.1
[+][-] X0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 39.40
[+][-] X1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.41
[+][-] X10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 39.50
[+][-] X11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 39.51
[+][-] X12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 39.52
[+][-] X13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 39.53
[+][-] X14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 39.54
[+][-] X15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 39.55
[+][-] X16 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 39.56
[+][-] X17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 39.57
[+][-] X18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 39.58
[+][-] X19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 39.59
[+][-] X2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 39.42
[+][-] X20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 39.60
[+][-] X21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 39.61
[+][-] X22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 39.62
[+][-] X23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 39.63
[+][-] X24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 39.64
[+][-] X25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 39.65
[+][-] X26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 39.66
[+][-] X27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 39.67
[+][-] X28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 39.68
[+][-] X29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 39.69
[+][-] X3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 39.43
[+][-] X30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 39.70
[+][-] X31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 39.71
[+][-] X4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 39.44
[+][-] X5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 39.45
[+][-] X6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 39.46
[+][-] X7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 39.47
[+][-] X8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 39.48
[+][-] X9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 39.49
[+][-] YES ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 39.1.3
----- End of DVASM listing -----
CopyRight Roberti & Parau Enterprises, Inc. 2021
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DVASM™ is a trademark of Roberti & Parau Enterprises, Inc.